Interconnect arrangement and method for fabricating an interconnect arrangement

ABSTRACT

An interconnect arrangement ( 100 ) has a first layer ( 101 ), a first layer surface ( 102 ), thereon at least two interconnects ( 104 ) having a second layer surface ( 105 ) essentially parallel to the first layer surface ( 102 ), thereon a respective second layer ( 106 ) for each interconnect ( 104 ), the second layers ( 106 ) of adjacent interconnects covering regions between the adjacent interconnects ( 104 ), and thereon a third layer ( 107 ), which completely closes off the regions between the adjacent interconnects ( 104 ) by means of coverage.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to an interconnect arrangement and a method forfabricating an interconnect arrangement.

Integrated circuit arrangements are produced with an ever higher packingdensity. The consequence of this is that there is an ever smallerdistance between interconnects in metallization planes. This means thatthere is a rise in capacitances which are formed between theinterconnects and lead to high signal propagation times, a high powerloss and crosstalk. To date, SiO₂ has principally been used asdielectric for insulation between the interconnects; its relativepermittivity ∈_(r)=3.9.

2. Description of the Related Prior Art

A number of methods for lowering the relative permittivity ∈_(r) andthus for lowering the capacitance between interconnects within aninterconnect plane are known, for example from [1], [2], or [3].

In accordance with the cited prior art, cavities are produced betweenthe interconnects within an interconnect plane. The insulatingdielectric which determines the capacitance between the interconnectsthus has a relative permittivity ∈_(r) which is almost equal to one. Inthis case, the interconnects themselves are enclosed by solid SiO₂layers at the top and bottom for the purpose of insulation.

BRIEF SUMMARY OF THE INVENTION

Since the capacitances of the underlying and overlying insulating layersalso contribute to a not inconsiderable extent to the total capacitancebetween adjacent interconnects within a layer and these insulatinglayers are still composed of solid SiO₂ material, the high relativepermittivity ∈_(r) of these insulating layers has a considerableinfluence on the total capacitance between the adjacent interconnects.

When using a low-k material for the insulating layer above theinterconnects, the cavities between adjacent interconnects are filledagain owing to the low viscosity of the low-k material. This againresults in a high relative permittivity ∈_(r) and thus a high totalcapacitance between adjacent interconnects.

Consequently, the invention is based on the problem of specifying aninterconnect arrangement and also a method for fabricating aninterconnect arrangement in which the cavities between theinterconnects, irrespective of the material used for the insulatinglayer which covers the interconnects, occupy a largest possible spaceand a smallest possible capacitance is thus achieved between theinterconnects on account of a small relative permittivity ∈_(r).

The problem is solved by means of an interconnect arrangement and alsoby means of a method for fabricating an interconnect arrangement havingthe features in accordance with the independent patent claims.

An interconnect arrangement has a first layer having a first layersurface, the first layer having a first insulation material, and atleast two interconnects situated on the first layer surface, having asecond layer surface essentially parallel to the first layer surface,the interconnects having a first material which is electricallyconductive. Furthermore, the interconnect arrangement has a second layermade of a second insulation material, which second layer is produced onthe second layer surface of each interconnect and projects beyond theinterconnect, the second layers of adjacent interconnects coveringregions between the adjacent interconnects. Finally, in the interconnectarrangement, a third layer covers the second layers, the third layerhaving a third insulation material and completely closing off theregions between the adjacent interconnects by means of coverage.

The interconnect arrangement can be designed in such a way that thethird layer is also arranged in part in the regions between adjacentinterconnects. However, in order to form a largest possible cavitybetween adjacent interconnects, an interconnect arrangement is preferredin which no part of the third layer is arranged in the regions betweenadjacent interconnects.

In a method for fabricating an interconnect arrangement, at least twointerconnects are applied on a first layer surface of a first layer, theinterconnects having a second layer surface essentially parallel to thefirst layer surface and sidewalls situated between the first layersurface and the second layer surface and also an electrically conductivefirst material and the first layer having a first insulation material.For each interconnect, a second layer made of a first insulationmaterial is produced on the second layer surface, each second layerbeing arranged in such a way that the second layer projects beyond theinterconnect and adjacent second layers are still not touched. Finally,a third layer made of a third insulation material is produced above thesecond layers, as a result of which an interconnect arrangement isformed between the first layer, the adjacent interconnects, the secondlayers and the third layer.

One advantage of the invention can be seen in the fact that, by means ofthe largest possible cavities as insulating layer between adjacentinterconnects, the relative permittivity ∈_(r) of the insulating layerbetween the adjacent interconnects deviates only little from one and thecapacitance between these interconnects is thus reduced. Theinterconnect arrangement enables a considerable reduction in the totalcapacitance within an integrated circuit. On account of leakage fieldsabove and below the interconnect arrangement, the effective relativepermittivity ∈_(r) for the entire interconnect arrangement isapproximately two. In this case, the value of the effective relativepermittivity ∈_(r) is dependent on the geometry of the entireinterconnect arrangement.

A further advantage of the interconnect arrangement according to theinvention is that the cavities between the interconnects do not have tobe fabricated by means of a selective deposition of a layer ofinsulating material which covers the cavities. Consequently, there isalso no need for time-consuming process optimization for such aselective deposition process. Primarily, the formation of menisci madeof the insulating material in the region of the cavities is avoided onaccount of the invention.

Preferably, there is a cavity between the first layer, the adjacentinterconnects, the second layers and the third layer, which cavity hasan electrically insulating effect between the adjacent interconnects.This cavity, in which air, vacuum or an insulating gas, for examplesulphur hexafluoride (SF₆), is present after completion of theinterconnect arrangement, thus has a relative permittivity ∈_(r) ofalmost equal to one. The interconnect arrangement thus has a smallcapacitance effect.

In a preferred development of the interconnect arrangement according tothe invention, at least one intermediate layer made of a second materialis situated between the first layer and the interconnects. Thisintermediate layer may be provided for example in order to provide abarrier for necessary etching processes during the fabrication of theinterconnect arrangement, in order that the first layer, usually havingsilicon dioxide (SiO₂), is not damaged.

The third insulation material is preferably a low-k material having arelative permittivity ∈_(r) in the range between 1 and 4. Since thethird layer, which completely covers the interconnect arrangement andeffects insulating screening in the vertical direction with respect tothe first layer surface, also makes a contribution to the totalcapacitance between adjacent interconnects, care should be taken toensure that the third insulation material used for the third layer alsohas a low relative permittivity ∈_(r).

In a preferred development of the interconnect arrangement according tothe invention, the third insulation material is a low-k material havinga relative permittivity ∈_(r) in the range between 1.5 and 3.

The second insulation material and/or the third insulation material ofthe interconnect arrangement preferably have silicon dioxide (SiO₂). Asan alternative, the second insulation material and/or the thirdinsulation material may also have silicon nitride (Si₃N₄) or an organicmaterial. Furthermore, a silicon-based oxide-nitride may also be used assecond insulation material and/or as third insulation material. In orderto obtain a low relative permittivity ∈_(r) when using these insulationmaterials, the respective insulation material should be applied inporous form. When using organic material, polymers are preferablyapplied in a methane environment during a PECVD process (PECVD=plasmaenhanced chemical vapour deposition).

In a preferred development of the interconnect arrangement according tothe invention, the first layer has at least two partial layers arrangedone above the other, the upper partial layer being patterned inaccordance with the regions between the interconnects in such a way thatthe upper partial layer is arranged below the interconnects and is atleast partly absent below the regions between the interconnects.Consequently, between adjacent interconnects, trenches are formed in theinsulating first layer. This arrangement has the advantage that theinterconnects are not applied directly on an insulation layer whichconnects the interconnects over the shortest route. An insulation layerwhich connects the interconnects over the shortest route promoteselectrical leakage fields between adjacent interconnects. This resultsin an unsatisfactory value for the effective relative permittivity ∈_(r)and thus for the total capacitance between adjacent interconnects. Apatterned upper partial layer makes it possible to enlarge theconnecting route between adjacent interconnects and thus to furtherreduce the effective relative permittivity ∈_(r). A patterned upperpartial layer thus enables a further reduction in the total capacitancebetween adjacent interconnects.

If the two partial layers have the same insulation material, an etchingstop layer made of a third material is preferably situated between theupper partial layer and the lower partial layer. In this case, the thirdmaterial is preferably essentially resistant to etchant which acts onthe first insulation material. Consequently, the patterning of the upperpartial layer can be fabricated by etching the upper partial layer withthe interconnects as mask. The etching is ended when the etching stoplayer is uncovered below the regions between adjacent interconnects.Consequently, the depth of the trenches between adjacent interconnectscan be set by means of the thickness of the upper partial layer.

In a method for fabricating an interconnect arrangement, before theapplication of the interconnects on the first layer surface, preferablyat least one intermediate layer made of a second material is produced onthe first layer surface. The intermediate layer is provided as a barrierfor etching processes during the fabrication of the interconnectarrangement, in order that the first layer, usually having silicondioxide (SiO₂) is not damaged. If an oxygen compound is chosen as firstinsulation material for the first layer, then a nitrogen compound, forexample a titanium-nitrogen compound, is preferably used as secondmaterial for the intermediate layer. If a titanium-nitrogen compound isused, the intermediate layer must also be removed on regions of thefirst layer surface which are not covered by the interconnects. This isusually achieved by means of an etching process, the interconnectsserving as mask for the intermediate layer. When using a nitrogencompound as first insulation material for the first layer, an oxygencompound is preferred as second material for the intermediate layer. Ifthe same material is used for the intermediate layer and also for thesubsequently fabricated spacers, then a thin, further intermediate layermade of a different material is preferably provided directly above theintermediate layer.

Preferably, trenches which reach at least partly into the first layerare produced between adjacent interconnects. This lengthens theconnecting route between adjacent interconnects and reduces theproduction of electrical leakage fields which adversely affect the totalcapacitance.

The first layer is preferably produced from an upper partial layer, anetching stop layer and a lower partial layer. The trenches betweenadjacent interconnects are then produced by the fact that, using theinterconnects as mask, the upper partial layer is removed below theregions between adjacent interconnects. The etching stop layer isuncovered in the process. If silicon dioxide (SiO₂) is chosen as firstinsulation material for the first layer and thus for the upper partiallayer and also for the lower partial layer, then silicon nitride(Si₃N₄), for example, can be used for the etching stop layer.

In a preferred development of the method according to the invention,spacers are produced on the sidewalls of the interconnects, the spacershaving a spacer material and being arranged in such a way that spacersof adjacent interconnects still do not touch one another. In this case,the spacers serve as auxiliary supports for the fabrication of thesecond layers, which project beyond the interconnects. The spacermaterial used is preferably silicon nitride (Si₃N₄) which is appliedconformally to the sidewalls of the interconnects. As an alternative, itis also possible to use another spacer material which can be appliedconformally and etched selectively with respect to the second layers andalso with respect to the first layer.

In a preferred embodiment of the method according to the invention, thespacers are produced on the sidewalls of the interconnects by means of aconformal deposition of spacer material and selective and anisotropicetching of the spacer material. Firstly, spacer material is depositedconformally over the interconnects and over regions of the first layersurface which are not covered by the interconnects. The spacer materialis subsequently etched anisotropically and selectively parallel to thesecond layer surface. This enables targeted fabrication and setting ofthe form of the spacers. The thickness of the deposited spacer materialis preferably set in such a way that the remaining gap between twoadjacent interconnects is only just not closed. Consequently, a thin airgap remains between the adjacent interconnects or the spacers situatedon the sidewalls thereof.

In the method according to the invention, the spacers are preferablyremoved again below the second layers. Since the spacers only serve asauxiliary supports for the fabrication of the second layers and wouldobstruct formation of the largest possible cavities between theinterconnects, the spacers are removed again after the fabrication ofthe second layers.

The second layers are preferably produced by means of a non-conformalmethod essentially parallel to the first layer surface above the secondlayer surface and the spacers. To that end, the second insulationmaterial of the second layers is deposited by means of a CVD process(CVD=chemical vapour deposition) with the smallest possible edgecoverage principally on the interconnects which are widened by thespacers. To that end, the CVD process is operated in thediffusion-determined regime, preferably by means of increasing thepressure. Instead of using a CVD process, it is also possible tofabricate the second insulation material for fabricating the secondlayers by means of a sputtering process. A second insulation materialthat has possibly penetrated deeply into the air gaps can be removedagain with the aid of a short isotropic etching, for examplewet-chemically or else in dry fashion in a downstream etching process.Such a downstream etching process is described in [4].

In a preferred embodiment of the method according to the invention, thespacer material of the spacers is etched away after the production ofthe second layers, a selective etching process being employed. In thiscase, the selective etching process is preferably isotropic. In thiscase, the air gap situated between adjacent spacers is necessary for theremoval of the spacers in order to offer the etchant an area of attackon the spacers. Possible etching processes are, for example, awet-chemical etching process or a downstream dry-etching process,described in [5] for a silicon dioxide (SiO₂), with high selectivity.

The third layer is preferably produced in such a way that firstly thirdinsulation material is deposited by means of a non-conformal method overthe second layers until cavities have formed between the first layer,the adjacent interconnects, the second layers and the third layer.Afterwards, third insulation material is deposited by means of aconformal standard method. During the non-conformal method, hardly anythird insulation material penetrates into the resulting cavities owingto the second layers acting in a screen-like manner. As a result, thesidewalls of the interconnects are covered with third insulationmaterial only to a very small extent, as a result of which the relativepermittivity ∈_(r) of the entire interconnect arrangement is influencedonly to an insignificant extent. In the case of relatively small featuresizes such as, for example, of a very large scale integrated circuit(VLSI circuit=very large scale integration), it is not possible toascertain any coverage of the sidewalls of the interconnects with thirdinsulation material.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the invention are illustrated in the figuresand are explained in more detail below. In this case, identicalreference symbols designate identical components.

In the figures:

FIG. 1 shows a cross section through an interconnect arrangement inaccordance with a first exemplary embodiment of the invention;

FIG. 2 shows a cross section through an as yet not completedinterconnect arrangement in accordance with FIG. 1 at a first timeduring the performance of the fabrication method in accordance with thefirst exemplary embodiment of the invention;

FIG. 3 shows a cross section through an as yet not completedinterconnect arrangement in accordance with FIG. 1 at a second timeduring the performance of the fabrication method in accordance with thefirst exemplary embodiment of the invention;

FIG. 4 shows a cross section through an as yet not completedinterconnect arrangement in accordance with FIG. 1 at a third timeduring the performance of the fabrication method in accordance with thefirst exemplary embodiment of the invention;

FIG. 5 shows a cross section through an as yet not completedinterconnect arrangement in accordance with FIG. 1 at a fourth timeduring the performance of the fabrication method in accordance with thefirst exemplary embodiment of the invention; and

FIG. 6 shows a cross section through an as yet not completedinterconnect arrangement at a first time during the performance of thefabrication method in accordance with a second exemplary embodiment ofthe invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 shows a cross section through an interconnect arrangement 100 inaccordance with a first exemplary embodiment of the invention.

The interconnect arrangement 100 has a substrate having a substratesurface formed as first layer surface 102 as first layer 101. Aninsulating material, silicon dioxide (SiO₂) in accordance with thisexemplary embodiment, is chosen as substrate material.

Situated on the first layer surface 102 are interconnects 104 made ofaluminium or copper with a respective intermediate layer 103 made of atitanium-nitrogen compound between the first layer surface 102 and theinterconnects 104. The interconnects 104 are bounded by a second layersurface 105 arranged parallel to the first layer surface 102 and alsosidewalls 108 which connect the first layer surface 102 and the secondlayer surface 105.

Situated on the second layer surface 105 of each interconnect 104 is asecond layer 106 made of silicon dioxide (SiO₂), which projects beyondthe respective interconnect 104. In this exemplary embodiment of theinvention, the second layers 106 have the form of screens covering theinterconnects 104. In this case, the second layers 106 cover regionsbetween adjacent interconnects 104. Since the second layers 106 ofadjacent interconnects 104 do not touch one another, the regions betweenthe adjacent interconnects 104 are not completely closed off by thesecond layers 106.

A third layer 107 made of silicon dioxide (SiO₂) covers the secondlayers 106 and thus completely closes off the regions between theadjacent interconnects 104. Consequently, cavities 109 enclosed by thefirst layer surface 102, the sidewalls 108 of the interconnects 104, thesecond layers 106 and the third layer 107 are situated between adjacentinterconnects 104.

During the fabrication of the third layer 107, silicon dioxide (SiO₂)was able to penetrate into the incompletely closed-off regions betweenthe adjacent interconnects 104. This caused a thin covering 110 of thesidewalls 108 of the interconnects 104 and also of that part of thefirst layer surface 102 not covered by the interconnects 104 withsilicon dioxide (SiO₂). The smaller the distance between adjacent secondlayers 106, the smaller the covering 110 of the sidewalls 108 of theinterconnects 104 and also of that part of the first layer surface 102not covered by the interconnects 104. In another exemplary embodiment ofthe invention (not illustrated in the figures), the second layers 106can also be fabricated with such a small spacing that no covering 110whatsoever is produced.

At the end of the interconnect arrangement 100, the last interconnect104 has an adjacent interconnect 104 only on one side. On the sidewithout an adjacent interconnect 104, the last interconnect 104 requireselectrical insulation from the environment. In this case, it is possibleto dispense with a low relative permittivity ∈_(r) for lack of a furtherelectrically conductive element representing a capacitance.Consequently, the last interconnect 104 is not electrically insulated bymeans of a cavity 109 like between adjacent interconnects 104, but bymeans of a terminating cavity 111 and a terminating insulating layer112.

The distance between adjacent interconnects 104 and the thickness of theinterconnects 104 should preferably be chosen in such a way that theinterconnect arrangement 100 has a sufficiently good carrying capabilityfor further layers and metallization planes arranged above theinterconnect arrangement 100. In accordance with this exemplaryembodiment, the interconnects 104 each have a width which is almostequal to the distance between adjacent interconnects 104. In accordancewith this exemplary embodiment, the interconnects 104 have a heightcorresponding to twice the width of the interconnects 104.

As an alternative, it is also possible to choose other dimensions forthe width, the height and/or the spacings of the interconnects 104.

A method for forming the interconnect arrangement 100 in accordance withthe first exemplary embodiment of the invention is described step bystep below.

FIG. 2 shows a cross section through an as yet not completedinterconnect arrangement 200 at a first time during the performance ofthe fabrication method in accordance with the first exemplary embodimentof the invention.

A substrate having a substrate surface formed as first layer surface 102is used as first layer 101. The substrate material is silicon dioxide(SiO₂). An intermediate layer 103 made of a titanium-nitrogen compoundis applied over the area of the first layer surface 102 using aconventional standard method. If the interconnect material is aluminium,the intermediate layer 103 serves as adhesion layer for theinterconnects 104 on the first layer 101, and if the interconnectmaterial is copper, the said intermediate layer serves as a barrieragainst copper diffusion in order to protect the first layer 101. If theinterconnect material is copper, the intermediate layer 103 may alsohave tantalum or a tantalum-nitrogen compound.

A plurality of interconnects 104 made of aluminium or copper are formedabove the intermediate layer 103 using known subtractive methods. Theinterconnects 104 terminate with a second layer surface 105 parallel tothe first layer surface 102 and have sidewalls 108 which connect thesecond layer surface 105 and the first layer surface 102.

During the fabrication of interconnects 104 made of copper, theso-called damascene technique may preferably be employed: firstly anauxiliary layer made of silicon dioxide (SiO₂) is applied on the area ofthe first layer surface 102 covered by the intermediate layer 103. Inthis case, the thickness of this auxiliary layer is set in accordancewith the desired height for the interconnects 104 to be fabricated.Using customary lithography and etching techniques, trenches are etchedinto the said auxiliary layer at the locations at which theinterconnects 104 are intended to be formed. These trenches have thedesired width and the desired distance from one another in accordancewith the interconnects 104 to be fabricated and reach down to theintermediate layer 103.

A barrier layer made, for example, of a tantalum-nitrogen compound andthen copper are then deposited over the auxiliary layer with thetrenches by means of customary metallization methods, the trenches beingoverfilled. In order to fabricate the second layer surface 105 parallelto the first layer surface 102, the copper overfilling the trenches andalso the barrier layer are removed areally by means of chemicalmechanical polishing. Finally, the auxiliary layer made of silicondioxide (SiO₂) is removed selectively with respect to copper by means ofetching until the intermediate layer 103 is reached. The intermediatelayer 103 made of a titanium-nitrogen compound acts as an etching stoplayer in this case. The interconnects 104 formed on the first layersurface 102 and the intermediate layer 103 remain.

The process for fabricating the interconnects 104 also includes thefinal etching of the intermediate layer 103 at all the locations whichare not covered by the interconnects 104. In this case, theinterconnects 104 serve as mask for the final etching. As a result, thefirst layer surface 102 is uncovered again between the interconnects104. Consequently, the intermediate layer 103 is now situatedexclusively between the interconnects 104 and the first layer surface102.

FIG. 3 shows a cross section through an as yet not completed cavitystructure 300 at a second time during the performance of the fabricationmethod in accordance with the first exemplary embodiment of theinvention.

Spacers 301 made of silicon nitride (Si₃N₄) are produced on thesidewalls 108 of the interconnects 104 conformally by means of conformaldeposition and subsequent etching, the spacers 301 being arranged insuch a way that spacers 301 of adjacent interconnects 104 still do nottouch one another. In this case, the spacers 301 serve as auxiliarysupports for the subsequent fabrication of the second layers 106 whichproject beyond the interconnects 104.

The selective and anisotropic etching of the conformally depositedspacer material enables targeted fabrication and setting of the form ofthe spacers 301. The thickness of the deposited spacer material ispreferably set in such a way that the remaining gap between two adjacentinterconnects 104 is only just not closed. Consequently, a thin air gap302 remains between the adjacent interconnects 104 or the spacers 301situated on the sidewalls 108 thereof.

FIG. 4 shows a cross section through an as yet not completedinterconnect arrangement 400 at a third time during the performance ofthe fabrication method in accordance with the first exemplary embodimentof the invention.

The second layers 106 made of silicon dioxide (SiO₂) are produced by anon-conformal method essentially parallel to the first layer surface 102above the second layer surface 105 and the spacers 301. To that end, thesilicon dioxide (SiO₂) is deposited by means of a CVD process with aslittle edge coverage as possible principally on the interconnects 104widened by the spacers 301. To that end, the CVD process is operated inthe diffusion-determined regime by means of increasing the pressure.Silicon dioxide (SiO₂) that has possibly penetrated deeply into the airgaps 302 is removed again by means of a short isotropic etching in adownstream etching process.

FIG. 5 shows a cross section through an as yet not completedinterconnect arrangement 500 at a fourth time during the performance ofthe fabrication method in accordance with the first exemplary embodimentof the invention.

Since the spacers 301 clearly essentially serve as auxiliary supportsfor the fabrication of the second layers 106 and obstruct formation ofthe largest possible cavities 109 between the interconnects 104, thespacers 301 are removed again after the fabrication of the second layers106. To that end, the silicon nitride (Si₃N₄) of the spacers 301 isetched away after the production of the second layers 106, a selective,isotropic etching process being employed. In this case, the air gap 302situated between adjacent spacers 301 is necessary for the removal ofthe spacers 301 in order to offer the etchant an area of attack in thespacers 301.

The largest possible interspaces 502 are now situated between thesidewalls 108 of adjacent interconnects 104, the first layer surface 102and the second layers 106. On account of the distance between them,respectively adjacent second layers 106 form openings 501 for theinterspaces 502, as a result of which the interspaces 502 are notcompletely closed off.

In order to form cavities 109 from the interspaces 502, the openings 501must now be closed. Therefore, the third layer 107 is produced in twoseparate method steps. Firstly, silicon dioxide (SiO₂) is deposited bymeans of a non-conformal method over the second layers 106 until theopenings 501 are closed and cavities 109 have formed between the firstlayer 101, the adjacent interconnects 104, the second layers 106 and thethird layer 107. Afterwards, silicon dioxide (SiO₂) is deposited bymeans of a conformal standard method in order to form a thick insulatingthird layer 107, as is illustrated in FIG. 1.

During the non-conformal method, hardly any silicon dioxide (SiO₂)penetrates into the resulting cavities 109 owing to the second layers106 acting in a screen-like manner. As a result, only a very smallcovering 110 of the sidewalls 108 of the interconnects 104 with silicondioxide (SiO₂) is produced, as a result of which the relativepermittivity ∈_(r) of the entire interconnect arrangement 100 isinfluenced only to an insignificant extent.

The interconnect arrangement 100, and thus also a last interconnect 104without an adjacent interconnect 104 beside one of its two sidewalls108, requires electrical insulation from the environment. Therefore, thethird layer 107 is formed above the entire interconnect arrangement 100.Since the last interconnect 104 has an adjacent interconnect 104 onlybeside one of its two sidewalls 108, the last interconnect 104 is notelectrically insulated by means of a cavity 109 like between adjacentinterconnects 104 but by means of a terminating cavity 111 and aterminating insulation layer 112. In this case, the terminatinginsulation layer 112 is produced as a side effect during the productionof the third layer 107 and thus likewise has silicon dioxide (SiO₂).

FIG. 6 shows a cross section through an as yet not completedinterconnect arrangement 600 at a first time during the performance ofthe fabrication method in accordance with a second exemplary embodimentof the invention.

The as yet not completed interconnect arrangement 600 of the secondexemplary embodiment differs from the as yet not completed interconnectarrangement 200 of the first exemplary embodiment only in the differentstructure of the first layer 101.

In accordance with this exemplary embodiment, the first layer 101 has anupper partial layer 601 made of silicon dioxide (SiO₂), an etching stoplayer 602 made of silicon. nitride (Si₃N₄) and a lower partial layer 603made of silicon dioxide (SiO₂). However, the first layer 101 may also becomposed of layers with different insulation materials. If differentinsulation materials with a different behaviour during an etchingprocess are used for the upper partial layer 601 and the lower partiallayer 603, it is possible to dispense with the etching stop layer 602.

The upper partial layer 601 is patterned in such a way that it isarranged below the interconnects 104 and is missing below the regionsbetween the interconnects 104. Situated in the upper partial layer 601are trenches 604 which reach down with uniform width between theinterconnects 104 from the second layer surface 105 as far as theetching stop layer 602.

The upper partial layer 601 can be patterned as follows: firstly, thesilicon dioxide (SiO₂) for the upper partial layer 601 is depositedareally. Afterwards, the interconnects 104 are fabricated, as alreadyexplained in the description with respect to FIG. 2. The trenches 604are subsequently etched into the areally deposited insulation material,the interconnects being used as an etching mask. In this case, by way ofexample, a wet-chemical downstream etching process may be employed. Inthe selection of the etching process to be employed, care should betaken to ensure that the etchant preferably acts on the silicon dioxide(SiO₂), and not on the interconnect material. The etching process isended as soon as the etching stop layer 602 is uncovered.

In accordance with this exemplary embodiment, the trenches 604 have adepth which preferably corresponds to 0.5 to 2 times the width of theinterconnects 104.

The further fabrication steps for an interconnect arrangement inaccordance with the second exemplary embodiment correspond to thefabrication steps described above for the first exemplary embodiment.The interconnect arrangement in accordance with the second exemplaryembodiment thus essentially corresponds to the interconnect arrangement100 in accordance with the first exemplary embodiment. The two exemplaryembodiments differ merely in the construction of the first layer 101.Thus, the cavities 109 in the second exemplary embodiment have, comparedwith the first exemplary embodiment, a larger volume owing to theexistence of the trenches 604.

To form an interconnect arrangement according to the invention inaccordance with the first or second exemplary embodiment, instead of thechosen insulation materials and the fabrication processes thereof, it isalso possible to use other insulating materials and fabricationprocesses.

By way of example, what are suitable as third insulation material forthe third layer 107 are insulating low-k materials having a low relativepermittivity ∈_(r) which are applied in a spin-on process and have a lowviscosity. In a spin-on process, the usually liquid material to beapplied is applied to the areas to be coated during spin-coating bymeans of spin-on.

If a low-k material having high viscosity is used as third insulationmaterial and, as a result, no third insulation material penetratesthrough the openings 501 into the interspaces 502, and so no covering110 is thus produced, the low-k material can be used directly toterminate the cavities 109 and thus to form the third layer 107.Otherwise, firstly silicon dioxide (SiO₂) for terminating the cavities109 is deposited non-conformally over the openings 501 and only then isthe low-k material deposited as third layer 107.

1. Interconnect arrangement, comprising: a first layer and a first layersurface, the first layer having a first insulation material; at leasttwo interconnects situated on the first layer surface, having a secondlayer surface essentially parallel to the first layer surface, theinterconnects having a first material which is electrically conductive;a second layer made of a second insulation material, which second layeris produced on the second layer surface of each interconnect andprojects beyond the interconnect, the second layers of adjacentinterconnects covering regions between the adjacent interconnects; athird layer covering the second layers, the third layer having a thirdinsulation material and completely closing off the regions between theadjacent interconnects by means of coverage; and a cavity between thefirst layer, the adjacent interconnects, the second layers and the thirdlayer, the cavity having an electrically insulating effect between theadjacent interconnects.
 2. Interconnect arrangement according to claim1, further comprising the third layer being arranged in part in theregions between adjacent interconnects.
 3. Interconnect arrangementaccording to claim 1, further comprising a cavity between the firstlayer, the adjacent interconnects, the second layers and the thirdlayer, the cavity having an electrically insulating effect between theadjacent interconnects.
 4. Interconnect arrangement according to claim1, in which at least one intermediate layer made of a second material issituated between the first layer and the interconnects.
 5. Interconnectarrangement according to claim 1, in which the third insulation materialis a low-k material having a relative permittivity ∈_(r) in the rangebetween 1 and
 4. 6. Interconnect arrangement according to claim 1, inwhich the third insulation material is a low-k material having arelative permittivity ∈_(r) in the range between 1.5 and
 3. 7.Interconnect arrangement according to claim 1, in which the secondinsulation material and the third insulation material have silicondioxide.
 8. Interconnect arrangement according to claim 1, in which thesecond insulation material and the third insulation material havesilicon nitride.
 9. Interconnect arrangement according to claim 1, inwhich the second insulation material and the third insulation materialhave an organic material.
 10. Interconnect arrangement according toclaim 1, in which the first layer has at least two partial layersarranged one above the other, the upper partial layer being patterned inaccordance with the regions between the interconnects in such a way thatthe upper partial layer is arranged below the interconnects and is atleast partly absent below the regions between the interconnects. 11.Interconnect arrangement according to claim 10, in which the two partiallayers have the same first insulation material and an etching stop layermade of a third material is situated between the upper partial layer andthe lower partial layer, the third material essentially being resistantto the etchant acting on the first insulation material.
 12. Method forfabricating an interconnect arrangement, comprising: applying at leasttwo interconnects on a first layer surface of a first layer, theinterconnects having a second layer surface essentially parallel to thefirst layer surface and sidewalls situated between the first layersurface and the second layer surface and also an electrically conductivefirst material and the first layer having a first insulation material;producing, for each interconnect, a second layer made of a firstinsulation material on the second layer surface, each second layer beingarranged in such a way that the second layer projects beyond theinterconnect and adjacent second layers are still not touched; andproducing a third layer made of a third insulation material above thesecond layers, as a result of which an Interconnect arrangement isformed between the first layer, the adjacent interconnects, the secondlayer and the third layer.
 13. Method according to claim 12, furthercomprising producing at least one intermediate layer made of a secondmaterial on the first layer surface, before applying the at least twointerconnects on the first layer surface.
 14. Method according to claim12, further comprising producing trenches which reach at least partlyinto the first layer between adjacent interconnects.
 15. Methodaccording to claim 14, further comprising: producing the first layerfrom an upper partial layer, an etching stop layer and a lower partiallayer; producing the trenches between adjacent interconnects using theinterconnects as a mask; removing the upper partial layer below theregions between adjacent interconnects; and uncovering the etching stoplayer.
 16. Method according to claim 12, further comprising producingspacers on the sidewalls of the interconnects, the spacers having aspacer material and being arranged in such a way that spacers ofadjacent interconnects still do not touch one another.
 17. Methodaccording to claim 16, further comprising: firstly depositingconformally, the spacer material; and etching the spacer materialanisotropically and selectively parallel to the first layer surface. 18.Method according to claim 16, further comprising removing the spacersagain below the second layers.
 19. Method according to claim 16, furthercomprising producing the second layers by means of a non-conformalmethod essentially parallel to the first layer surface above the secondlayer surface and the spacers.
 20. Method according to claim 16, furthercomprising etching away the spacer material of the spacers after theproduction of the second layers, by use of a selective etching process.21. Method according to claim 20, in which the selective etching processis isotropic.
 22. Method according to one of claims 12 to 21, furthercomprising producing the third layer in such a way that firstly thirdinsulation material is deposited by means of a non-conformal method overthe second layers until cavities have formed between the first layer,the adjacent interconnects, the second layers and the third layer, andthird insulation material is subsequently deposited by means of aconformal standard method.